A high-energy particle strike to a sensitive node in a micro-electronic device may result in an error in the device output or operation. The error, sometimes referred to as a soft error or a single event upset (SEU) may be, for example, a change of logic state in the circuit.
Attempts to minimize effects of the particle strike or to avoid an SEU generally fall into categories of SEU avoidance, SEU masking, and SEU management. SEU avoidance techniques may focus on reduction on the severity of the environment; reduction in charge generation and/or collection; and elimination or reduction in circuit response to collected charge. Such efforts, however, may significantly decrease the circuit's native performance. Other considerations may include high area and power overheads. Further, it may be difficult to reuse a design for low power applications that do not have a need for redundancy.
SEU masking techniques may focus on informational redundancy, including error detection and correction coding, and spatial and temporal redundancy. Such efforts, however, may result in increased area or delay overhead.
SEU management techniques may focus on fault detection, fault containment, and system recovery. Such efforts, however, may result in inserting redundant elements and significant area and delay overhead.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.